Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. MOS transistors include a gate dielectric overlying a channel region of a semiconductor substrate and a gate electrode situated above the gate dielectric. Source and drain regions are formed in the substrate on either side of the channel. Gate dielectric and gate electrode layers (e.g., silicon dioxide (SiO2) and poly-silicon, respectively) are initially formed over the substrate and the gate electrode is patterned to form a gate structure overlying the channel region of the substrate, after which the source/drain regions are doped with n or p-type impurities.
FIG. 1 illustrates a portion of a fabrication process flow 2 relating to gate structure fabrication and FIGS. 2A–2C illustrate a MOS transistor 50 at different stages of fabrication having poly-silicon gate electrode material and SiO2 gate dielectric material. At step 4 in the process 2, a gate dielectric is formed over the substrate, after which poly-silicon gate electrode material is deposited at 6. As shown in FIG. 2A, a thin gate dielectric oxide 62 (e.g., SiO2) is formed over a silicon substrate 54 between field oxide structures 56, and poly-silicon material 68 is formed over the dielectric 62 and the field oxide 56. A gate etch process 58 is then performed using a mask 59 in FIG. 2A (step 8 in FIG. 1) to form a patterned gate structure as shown in FIG. 2B. A drain extension implantation is performed (step 10 in FIG. 1) to introduce dopants into source/drain regions 60 outlying the patterned gate structure. Any gate dielectric material 62 remaining over the source/drains 60 that may have been damaged by the etching 58 or the dopant implantation is removed (e.g., stripped) after the implantation.
A reoxidation process 61 is performed (step 12 in FIG. 1) to grow or deposit an oxide encapsulation layer 70 over the top and sidewalls of the patterned gate structure, and over the source/drain regions 60 of the substrate 54, as shown in FIG. 2B. This reoxidation 61 serves to reoxidize the upper surface of the substrate 54 in the source/drain regions 60. The reoxidation 61 also encapsulates the patterned gate structure by forming SiO2 70 over the top and sidewalls of the poly-silicon gate electrode 68 and along any exposed portions of the gate dielectric 62 under the electrode 68. The encapsulation layer 70 may inhibit boron dopant out-diffusion from the p-doped poly-silicon gate electrodes 68 during subsequent formation of inter-level dielectrics, reduce gate-to-drain overlap capacitance, and strengthen the gate dielectric 62 at the edge of the poly-silicon gate electrode 68. As shown in FIG. 2C, sidewall spacers 72 are then formed along the sidewalls of the patterned encapsulated gate structure (step 14 in FIG. 1), and deeper source/drain implants are performed to further define the source/drains 60. The source/drains are silicided to form source/drain contacts 74 and the top of the poly-silicon gate electrode 68 is silicided to form a gate contact 66, after which interconnect and other back-end fabrication processing (not shown) is performed.
In operation, the gate electrode 68 is energized to create an electric field in the channel region of the substrate 54, thereby rendering a portion of the channel conductive and allowing electrons to travel through the channel between the source/drains 60. The threshold voltage (Vt) of the transistor 50 is the gate voltage value required to render the channel conductive by formation of an inversion layer at the surface of the semiconductor channel. The threshold voltage Vt is dependent upon the flat-band voltage, which in turn depends on the work function difference between the gate and the substrate materials, as well as on surface charge. To set Vt values, the work functions of the poly-silicon gate electrodes 68 and the corresponding channel material (e.g., silicon) are independently tuned or adjusted for p-channel and n-channel transistors 50 (PMOS and NMOS) through gate and channel doping (e.g., gate and channel engineering), respectively. Because the work function of poly-silicon can be easily changed while being rendered conductive by appropriate dopant implantation, poly-silicon has thusfar been widely employed in forming gate electrodes 68, particularly in fabricating complementary MOS (CMOS) devices having both NMOS and PMOS transistors 50.
The gate dielectric 62 is an insulator material, typically SiO2 or other dielectric, that operates to prevent large currents from flowing from the gate electrode 68 into the channel when a gate voltage is applied, and allows an applied gate voltage to establish an electric field in the channel region in a controllable manner. Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions 60 under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of SiO2 gate dielectric 62 that is formed over the semiconductor surface. However, limitations on the extent to which SiO2 gate dielectric thicknesses can be reduced have lead to increased usage of so-called high-k dielectric materials having dielectric constants greater than that of SiO2. High-k gate dielectrics can be formed in a thicker layer than scaled SiO2 while producing equivalent field effect performance. However, certain high-k dielectric materials may be damaged during gate etching.
Another shortcoming of the conventional MOS transistor 50 is known as poly-silicon depletion. Poly-silicon depletion occurs when annealing or other thermal processing following implantation of dopants into poly-silicon gate electrode material 68 is insufficient to activate the implanted impurities at the poly-silicon gate dielectric interface 68. In this situation, a bottom portion of the poly-silicon gate electrode 68 near the gate dielectric 62 is “depleted” of charges, and acts as an insulator. The depleted portion of the gate contact and the gate dielectric operate as series connected capacitors, resulting in a reduced effective gate capacitance, which reduces the drive current capability of the device. Consequently, poly-silicon depletion causes reduction in device performance and leads to poor unscalable devices, where poly-silicon depletion problems become more significant as device dimensions continue to be scaled.
Accordingly, attention has recently been directed to using metal gate electrodes in MOS transistors to avoid the effects of poly-silicon depletion. However, metal gate materials may also be damaged by gate patterning (e.g., etching, wet cleans, etc.) operations, wherein the use of conventional reoxidation encapsulation techniques can actually degrade the damaged metal. Furthermore, use of traditional oxidation processes in forming an encapsulation layer for patterned metal gate structures may itself cause unwanted oxidation of the metal material, leading to further degradation of device performance. For example, exposing a gate stack structure having a titanium nitride (TiN) layer to a conventional reoxidation process causes formation of titanium oxynitride (TiON) along the gate sidewall, which effectively increases the capacitance of the gate electrode by formation of a dielectric in a portion of the gate electrode. Furthermore, as discussed above, traditional reoxidation processes may cause formation of low-k dielectrics along the sidewall of high-k gate dielectric layers in the gate stack. Accordingly, there is a need for improved gate encapsulation structures and techniques by which metal and other gate structures may be encapsulated after patterning.